This project is only open to UK Nationals.

Aim

The project proposal is to investigate hardware solutions for high-throughput low-latency data interconnect between real-time FPGA processors and streaming GPGPU devices, using STAP / adaptive beamforming as a test-case both for the processing involved and to inform the data rates.

Objectives

1. Investigate hardware solutions for high-throughput low-latency data interconnect between real-time FPGA processors and streaming GPGPU devices, using STAP / adaptive beamforming as a test-case both for the processing involved and to inform the data rates.
2. Demonstrate initial streaming data transfer rates of at least 500 Gb/s (sustained) between FPGA and GPU devices, with a goal of at least 2 Tb/s, ultimately. This work would encompass all the necessary firmware and software on the FPGA, GPU, embedded CPU, and potentially CPU controllers. This work could be carried out initially with a representative mock data load.
3. Once the primary work is completed, the candidate would investigate optimisations of the DSP and GPU-side algorithms themselves for both performance and power, but the project is intended to be primarily hardware focused rather than algorithm optimisation.

Description

Multi-channel adaptive beamforming techniques such as STAP offer benefits for modern airborne radars but are computationally expensive. GPGPUs are used extensively in High Performance Computing (HPC) and can also provide the large amount of compute required for real-time adaptive processing. However, these are designed to interface with CPU processing resources over data-buses such as PCI-express, whereas the digitisers in (wide-band, multi-channel) radar receivers typically interface with FPGA devices.

Furthermore, there is a significant gap in throughput between what is desirable and what is achievable for FPGA to GPU data transfers over PCI-Express.

This research is of great strategic importance to Leonardo UK, and more widely is one of the enabling technology for truly next-generation digital antennas. Through working on an application which is at the cutting edge of defence and aerospace research, the candidate will develop skills in digital interfacing and hardware design, along with experience to HPC, all of which are highly sought after in industry.

This problem is also highly relevant to other high-speed data acquisition and processing problems, e.g. those found in medical imaging and a wide range of HPC workloads.

Candidates should have a good degree in Electronics Engineering, computer science or equivalent. Experience with implementing algorithms on FPGAs, GPUs, and/or HPC. A willingness to learn new technologies and techniques.